FIG. 1 illustrates a typical conventional transistor device 100 comprising a semiconductor substrate 101, a gate electrode 103, source/drain regions 105, sidewall spacers 107, and source/drain contact 109. The gate electrode 103 is formed on the surface of semiconductor substrate 101 and typically includes a thin silicon dioxide layer 111 and a polysilicon layer 113. Sidewall spacers 107 are formed on the side surfaces of the gate electrode and block implants when forming source/drain regions 105.
As the dimensions of transistor devices continue to shrink, parasitic parameters that were previously considered benign now adversely affect the performance of the transistor and the circuit in which it is used. Among these parameters is the miller capacitance, which is used to describe the capacitance 115 formed between a transistor's gate electrode 103 and the contact 109 to the transistor's source/drain region 105. Current technology produces transistor devices with a miller capacitance of 0.26-0.3 femtoFarads. The reduction of design features makes it highly desirable to reduce the miller capacitance down to 0.18-0.23 femtoFarads.
Nitrides, such as silicon nitride, are conventionally employed as sidewall spacers, and typically have a dielectric constant of about 6 to 7, with the dielectric constant of air being 1. The miller capacitance is heavily dependent upon the dielectric constant of the spacer material. The lower the dielectric constant of the spacer material, the lower the miller capacitance.
Oxides, such as silicon oxide, typically have a dielectric constant of about 3.9 to 4.2, and have been previously employed as spacers. However, oxide spacers have proven problematic in limiting the process flow for forming complex transistors. For example, oxide spacers severely limit the formation of multiple implants, formation of complex spacer structures, and effective utilization of etch selectivity with other films in the circuit. Therefore, silicon nitride has become the material of choice for sidewall spacers. However, the use of silicon nitride spacers prevents effective reduction of the miller capacitance.
A need therefore exists for spacer formation technology enabling the formation of complex transistors without adversely impacting process flow.